1. Field of the Invention
This invention relates to a semiconductor memory incorporating a test circuit and more particularly to that having decision function of whether the write/read operations of data into/from memory cell arrays have been normally accomplished.
2. Description of the Prior Art
The semiconductor memory performs a decision test in the procedure of carrying out write/read operations of data in/from each memory cell of the memory cell array, and deciding, with the readout data, whether the write/read operations have been normally accomplished, or not. In the use of usual write and read circuits and nothing else for this test, increasing capacity of semiconductor memory reflects exponential prolongation of test time, making it extremely difficult to practice the test. The longer the test time, the more the cost of the semiconductor memory and the system involving it. At present, therefore, most of megabit scale semiconductor memories are provided with a test circuit-incorporating semiconductor memory for shortening test time.
A test circuit-incorporating semiconductor memory of conventional type is provided with a plurality of memory cell arrays. With the work of the built-in test circuit, a decision test is performed in the procedure of carrying out write/read operations of the same data in/from each memory cell array, and deciding whether the write/read operations have been normally accomplished, or not, according to if the readout data are identical with each other, or not.
More detailed description will be given under:
In the normal mode, on changing to the write operation, an external write data is input and written into a selected memory cell array in the memory cells. In the read operation, one of selectively readout data from each memory cell array is selected, amplified and output to the external.
The supply of write data into each memory cell array and the amplification of the data read from each memory cell array are carried out by means of the respective corresponding data amplifier.
In the test mode, on changing to the write operation, an external write data is input and written at the same time into all the memory cell arrays. In the read operation, the data read from each memory cell array is amplified by the respective corresponding data amplifier and supplied to a test circuit. The test circuit decides whether all the data supplied thereinto are identical with each other, or not. If all the data are identical, decision that the write/read operations are normal is signaled. If at least one of the data is different from the others, decision that one or both of the operations is abnormal is signaled.
After the write/read operations of the same data into/from memory cell arrays, all these data are amplified and supplied to the test circuit as stated above. For implementing the first operation memory cell arrays, are needed data amplifiers and data buses, the three kinds being correspondent to each other in one-to-one-to-one. For example, four data buses are required if the numbers of memory cell arrays and data amplifiers are four each.
On the other hand, assuming that the respective numbers of memory cell arrays, data amplifiers and data buses are fixed, the more the memory capacity is, the longer the test time is. For shortening test time, accordingly, it is necessary to increase the respective numbers of memory cell arrays, data amplifiers and data buses and to decrease memory capacity per memory cell array. For example, assuming that for 1-megabit memory capacity, the numbers of memory cell arrays, data amplifiers and data buses are four each, it follows that with increasing memory capacity as 4, 16 and 64 bits, all the respective numbers of memory cell arrays, data amplifiers and data buses required for identical test time increase as 16, 64 and 256.
The areas on a semiconductor chip that memory cell arrays and data amplifiers occupy are proportional to the memory capacity. On the other hand, the area of data buses on the semiconductor chip is proportional to only the number of them independent of memory capacity. In such-type test circuit-incorporating semiconductor memory, it is a matter of course that with increasing memory capacity, the required areas of memory cell arrays and data amplifiers increase. For shortening test time, it is needed to increase the number of data buses, accompanied by increases in the area of them, and consequently larger area of the semiconductor chip.
The output terminal of each data amplifier is connected to the corresponding data buses, respectively, thereby allowing the parasitic capacity of the wiring connecting between the data amplifier and the corresponding data bus and the parasitic capacity of the data bus itself to connect to the output terminal of each data amplifier, resulting in the delay of the output data from the data amplifier. Such parasitic capacity is the greatest on the data bus path located at the farthest from the data amplifier, and increases with larger in the number of data buses. In general, operation speed is limited by the data of the longest delay time. Increase in the number of data buses to shorten test time therefore reflects lower read operation speed.